Zero indication forwarding for floating point unit power reduction

US8578196B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Harry Barowski · Balingen, DE
• Maarten J. Boersma · Holzgerlingen, DE
• Silvia M. Mueller · Altdorf, DE
• Tim Niggemeier · Laatzen, DE
• Jochen Preiss · Eppelheim, DE

Key dates

• Filing date: Jul 18, 2012
• Grant date: Nov 5, 2013
• Expiry date: Jul 18, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.