Integrated circuit contact structure and method
US8580628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Feb 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.