Methods for fabricating integrated circuits using non-oxidizing resist removal

US8586440B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Steven Langdon · Dresden, DE
• Thomas Feudel · Radebeul, DE

Key dates

• Filing date: Jul 27, 2011
• Grant date: Nov 19, 2013
• Expiry date: Feb 27, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.