Semiconductor chip and semiconductor package with stack chip structure
US8592952B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Dec 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip and semiconductor package with stack chip structure include align patterns. The align patterns are formed of magnetic materials having opposite polarities on the top and bottom of the semiconductor chip. Thus, when the plurality of chips are stacked on the substrate in order for the packaging, the semiconductor chips may be exactly aligned by the magnetic force between the align patterns of the vertically stacked chips. The semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.