Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices
US8598005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.