Integrated circuit having pitch reduced patterns relative to photoithography features

US8598632B2 · kind B2 · utility

Assignee

• Round Rock Research, LLC · US

Inventors

• Luan C. Tran · Meridian, US
• William T. Rericha · Boise, US
• John Lee · Boise, US
• Ramakanth Alapati · Boise, US
• Sheron Honarkhah · Boise, US
• Shuang Meng · Austin, US
• Puneet Sharma · Boise, US
• Jingyi Bai · San Jose, US
• Zhiping Yin · Boise, US
• Paul A. Morgan · Kuna, US
• Mirzafer Abatchev · Boise, US
• Gurtej S. Sandhu · Boise, US
• D. Mark Durcan · Boise, US

Key dates

• Filing date: Jun 22, 2012
• Grant date: Dec 3, 2013
• Expiry date: Jun 22, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3088
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.