Asymmetric mesh NoC topologies
US8601423B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.