Memory diagnostics system and method with hardware-based read/write patterns
US8607104B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.