Method of fast analog layout migration
US8607182B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.