Method for fabricating a neo-layer using stud bumped bare die
US8609473B2 · kind B2 · utility
0Cited by
7References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jan 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.