Spacer protection and electrical connection for array device
US8623714B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Apr 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.