Semiconductor package for selecting semiconductor chip from a chip stack
US8624375B2 · kind B2 · utility
1Cited by
2References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.