Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

US8629500B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Juergen Holz · Munich, DE
• Ronald Kakoschke · Birkenfeld, DE
• Thomas Nirschl · Putzbrunn, DE
• Christian Pacha · Birkenfeld, DE
• Klaus Schruefer · Baldham, DE
• Thomas Schulz · Austin, US
• Doris Schmitt-Landsiedel · Ottobrunn, DE

Key dates

• Filing date: Dec 9, 2005
• Grant date: Jan 14, 2014
• Expiry date: Oct 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.