Method and device employing polysilicon scaling

US8637918B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Shenqing Fang · Fremont, US
• Chun Chen · San Jose, US
• Wenmei Li · San Jose, US
• Inkuk Kang · San Jose, US
• Gang Xue · Beijing, CN
• Hyesook Hong · Allen, US

Key dates

• Filing date: Nov 10, 2011
• Grant date: Jan 28, 2014
• Expiry date: Nov 10, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.