Operating method for non-volatile memory unit
US8638589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.