Fin-transistor formed on a patterned STI region by late fin etch
US8652889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jun 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
Abstract
When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.