Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
US8658523B2 · kind B2 · utility
15Cited by
4References
4Claims
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Key dates
| Filing date | Sep 9, 2010 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Feb 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.