Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier
US8664081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.