Highly selective spacer etch process with reduced sidewall spacer slimming
US8664125B2 · kind B2 · utility
8Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.