Chip package and a method for manufacturing a chip package
US8669655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.