Method to improve wet etch budget in FEOL integration

US8679941B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jason E. Cummings · Smithfield, US
• Lisa F. Edge · Watervliet, US
• Balasubramanian S. Haran · Watervliet, US
• David V. Horak · South Burlington, US
• Hemanth Jagannathan · Niskayuna, US
• Sanjay C. Mehta · Niskayuna, US

Key dates

• Filing date: Mar 16, 2012
• Grant date: Mar 25, 2014
• Expiry date: Mar 16, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.