Single event latch-up prevention techniques for a semiconductor device

US8685800B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Jianan Yang · Austin, US
• James D. Burnett · Austin, US
• Brad J. Garni · Austin, US
• Thomas W. Liston · Austin, US
• Huy Van Pham · Austin, US

Key dates

• Filing date: Jul 27, 2012
• Grant date: Apr 1, 2014
• Expiry date: Jul 27, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.