Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
US8685817B1 · kind B1 · utility
8Cited by
11References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 19, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.