Reference cell configuration for sensing resistance states of MRAM bit cells
US8687412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Apr 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.