Providing timing-closed FinFET designs from planar designs

US8689154B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Mahbub Rashed · Cupertino, US
• David Doman · Austin, US
• Dinesh Somasekhar · Hillsboro, US
• Yan Wang · Beijing, CN
• Yunfei Deng · Berkeley, US
• Navneet Jain · Milpitas, US
• Jongwook Kye · Pleasanton, US
• Ali Keshavarzi · Portland, US
• Subramani Kengeri · Norwood, US
• Suresh Venkatesan · Los Gatos, US

Key dates

• Filing date: Apr 13, 2012
• Grant date: Apr 1, 2014
• Expiry date: Apr 13, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.