Semiconductor device with strain-inducing regions and method thereof

US8698243B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Jan Hoentschel · Dresden, DE
• Thilo Scheiper · Dresden, DE

Key dates

• Filing date: Jul 29, 2013
• Grant date: Apr 15, 2014
• Expiry date: Jul 29, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8325
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.