Patent · US Active

Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging

US8698312B2 · kind B2 · utility

0Cited by

6References

19Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

James Werking · Dresden, DE
Frank Feustel · Dresden, DE
Christian Zistl · Dresden, DE
Peter Huebler · Coswig, DE

Key dates

Filing date	Jan 31, 2005
Grant date	Apr 15, 2014
Priority date	—
Expiry date	Apr 14, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/12044
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.