Integrated circuit package system with exposed interconnects
US8704349B2 · kind B2 · utility
7Cited by
228References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2006 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Aug 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.