Integrated circuit packaging system having a cavity
US8704365B2 · kind B2 · utility
10Cited by
53References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jul 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.