Semiconductor process
US8709930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Apr 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
Abstract
A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.