Integrated circuit packaging system with coupling features and method of manufacture thereof
US8710670B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jan 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.