Reduced pattern loading using silicon oxide multi-layers
US8716154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28556
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.