Method for reading and writing multi-level cells
US8724380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of MTJ memory elements coupled in series. The method detects the resistance states of individual MTJ memory elements in an MLC by sequentially writing each memory element to the low resistance state in order of ascending parallelizing write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.