Methods of forming a three-dimensional semiconductor device with a nanowire channel structure

US8728885B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Daniel T. Pham · Clifton Park, US
• Jody A. Fronheiser · Delmar, US
• William J. Taylor, Jr. · Clifton Park, US

Key dates

• Filing date: Dec 27, 2012
• Grant date: May 20, 2014
• Expiry date: Dec 27, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.