High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction
US8735302B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.