Low read current architecture for memory
US8737151B2 · kind B2 · utility
6Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.