Patent · US Active

Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

US8748268B1 · kind B1 · utility

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8Claims
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Key dates

Filing dateDec 20, 2012
Grant dateJun 10, 2014
Priority date
Expiry dateDec 20, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/661
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.