Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

US8765542B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Joachim Patzer · Rohrbach, DE
• Frank Seliger · Dresden, DE
• Markus Lenski · Dresden, DE
• Stephan Kronholz · Dresden, DE

Key dates

• Filing date: Feb 13, 2013
• Grant date: Jul 1, 2014
• Expiry date: Feb 13, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

One method disclosed includes forming a gate structure of a transistor above a surface of a semiconducting substrate, forming a sidewall spacer proximate the gate structure, forming a sacrificial layer of material above the protective cap layer, sidewall spacer and substrate, forming an OPL layer above the sacrificial layer, reducing a thickness of the OPL layer such that, after the reduction, an upper surface of the OPL layer is positioned at a level that is below a level of an upper surface of the protective cap layer, performing a first etching process to remove the sacrificial layer from above the protective cap layer to expose the protective cap layer for further processing, performing a second etching process to remove the protective cap layer and performing at least one process operation to remove at least one of the OPL layer or the sacrificial layer from above the surface of the substrate.