Processor with increased efficiency via early instruction completion
US8769247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2011 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | May 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.