Fabrication method for embedded magnetic memory
US8772051B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2013 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Feb 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
A wafer has a memory area and a logic area and a topmost metal contact layer on the surface covered with dielectric and etch stop layers. In the memory area, vias are opened through the dielectric and etch stop layers to topmost metal contact layer. In the logic area, evenly distributed dummy fill patterns are opened through a portion of the dielectric and etch stop layers. These are filled with a metal layer and planarized, forming a flat wafer surface. MTJ elements in the memory area and dummy elements in the logic area are formed on the flat surface. The dummy MTJ elements and fill patterns are etched away in the logic area. Metal connections are formed to the topmost metal contact layer in the logic area and top lead connections to MTJ elements are formed in the memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.