Techniques for the fabrication of thick gate dielectric
US8778750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jul 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.