Semiconductor device with chip having low-k-layers
US8786105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2013 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Jan 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.