Method and structure for shallow trench isolation to mitigate active shorts
US8790991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2011 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.