Stress mitigating amorphous SiO2 interlayer
US8796121B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02483
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.