Creating an embedded reram memory from a high-K metal gate transistor structure
US8803124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Feb 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.