Transistor with controllable compensation regions

US8803205B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Armin Willmeroth · Friedberg, DE
• Franz Hirler · Isen, DE
• Hans Weber · Villach, AT
• Michael Treu · Villach, AT

Key dates

• Filing date: May 31, 2012
• Grant date: Aug 12, 2014
• Expiry date: May 31, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/512

Abstract

A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.