Method to reduce magnetic film stress for better yield

US8803293B2 · kind B2 · utility

Assignee

• Headway Technologies, Inc. · US

Inventors

• Tom Zhong · Saratoga, US
• Kenlin Huang · Fremont, US
• Chyu-Jiuh Torng · Pleasanton, US

Key dates

• Filing date: May 11, 2012
• Grant date: Aug 12, 2014
• Expiry date: May 12, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/01

Abstract

A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.