Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch
US8809194B2 · kind B2 · utility
5Cited by
18References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jun 14, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/976
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.