Patterned dummy wafers loading in batch type CVD
US8809206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2011 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | May 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.