Transistor with reduced parasitic capacitance
US8809962B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.